As advanced continue to be made in the area of semiconductor memory devices, high capacity and low cost is increasingly important. Small memory cells arranged in large arrays that are stacked three dimensionally is an approach to building density. Memory cell designs having a footprint no larger than 4F2 are increasingly desired to provide high density. However, because of parasitic resistance in bit lines and word lines, increasingly large arrays result in non-negligible voltage drops across these bit lines and word lines. When building 3-D memory arrays, these voltage drops are compounded by the many layers. Furthermore, the many layers must be interconnected to logic built into the substrate and the associated cost of masks, lithography and processing increases the cost per bit.
Low Impedance Paths to and from Memory Cell Elements
In the parlance of semiconductors, resistance of a wire is often quoted “per square.” As is well known to those in the art, a square of material is a portion of that material having equal measures in both the x and y directions. Material resistance is quoted in squares (i.e., ohms per square or Ω/□) because as long as the x and y direction measurements are equal and the material thickness is unchanged (where thickness is measured in the z direction), the resistance across that square of material will be the same regardless of the size of that square. With this in mind, the resistances of a wire of such material is equal to the length of that wire (measured in squares—i.e., the number of squares that the wire is long) multiplied by the resistance per square.
Referring to FIG. 1, a single memory cell from a memory array is shown with its associated Word Line and Bit Line. In this figure, a Bit Line (BL) is formed in the substrate material. Doped semiconductor material can have resistance values ranging from 70 Ω/□ to 100 Ω/□. A Bit Line in a memory tile that is 1000 memory cells by 1000 memory cells can therefore have an end-to-end resistance of 14 kΩ to 20 kΩ (2000 squares×70 Ω/□ to 100 Ω/□ where each memory cell is two squares across to account for the width of the orthogonal Word Line, WL, and the space between the WL's) with the average resistance to any memory cell (one in the middle of the array) being approximately 8.5 ka From Ohms Law (V=IR), if a current through the memory cell is 100 μA, the voltage drop across this average resistance will be approximately 0.85 volts and to a cell at the far end of the line, 1.7 volts. If three layers of memory cells as shown in FIG. 2 were to pass a current of 100 μA, this voltage drop would triple to 2.55 volts—a large parasitic voltage for an integrated circuit memory array (5.1 volts to the far end).
Similarly in FIG. 1, a Word Line (WL) is formed in the top connected metal material. Metals can have resistance values ranging from 0.1 Ω/□ to 0.3 Ω/□. A Word Line in a memory tile that is 1000 memory cells by 1000 memory cells can therefore have an end-to-end resistance of 100 Ω to 300 Ω (2000 squares×0.1 Ω/□ to 0.3 Ω/□ where each memory cell is two squares long to account for the width of the orthogonal Bit Line, BL, and the space between the BL's) with the average resistance to any memory cell (one in the middle of the array) being approximately 100Ω. Again from Ohms Law, if a current through the memory cell is 100 μA, the voltage drop across this average resistance will be approximately 0.01 volts. Even though this WL voltage drop is small, it contributes to the possibility of sneak paths forming. A sneak path is when sneak current flows into the read sense circuit along paths other than the intended path through an addressed memory element (i.e., by passing through unaddressed memory elements). While a sneak current is often very small, in a very large memory array, and in particular a very large memory array that is three dimensionally stacked, the sum of all sneak currents can be sufficient to make reading (i.e., measuring) the current passing through an addressed memory cell problematic. A solution is needed for a 3-D memory array that minimizes or eliminates the impact of sneak currents.
Bipolar Operation of Memory Cell Elements in Unipolar Arrays
In addition to the resistance problems, cross-point arrays will typically have unipolar (i.e., diode or BJT) select devices. Diodes generally limit current flow to one direction resulting in unipolar memory cell operation. While some memory cell materials, such as phase change materials, work well in a unipolar environment, other materials such as resistive RAM (ReRAM) materials, while they can be made to work in a unipolar environment (if formed filaments are removed by fuse-blowing those filaments), can work better in a bipolar environment.
Memory Layer Planes Interconnect to Substrate
Another problem to address with large 3-D memory arrays is the interconnection of the various layers with the substrate whereby the many layers must be interconnected to logic built into the substrate and the associated costs of masks, lithography and processing increases the cost per bit. One approach to addressing these costs is stair step formation through repeated etching. Recent 3-D NAND solutions illustrate this technique (e.g., see http://thememoryguy.com/3d-nand-how-do-you-access-the-control-gates/).
Referring to FIG. 3, the layers of the memory array (consisting of alternating layers of dielectric, such as silicon dioxide, and conductive material, such as polysilicon) are deposited on top of a wafer having the array's control logic already formed in its surface (FIG. 3a). A thicker hard mask material on the surface is photolithographically patterned and anisotropically etched (etchmask1) to create an opening at the edge of the array where vias are to be formed (FIG. 3b). Next, the first oxide layer is etched (etchOx1) using an anisotropic oxide etch that stops on silicon (FIG. 3c), followed by etching the first poly layer (etchPoly1) using an anisotropic silicon etch that stops on oxide (FIG. 3d). Once the surface is initially set up in this way, the hard mask is etched sideways with an isotropic etch in a step called a “pull-back” etch (etchMask2) as is shown in FIG. 3e; the hard mask material thickness is selected to ensure that some hard mask material will survive the entire etch process. The pull-back etch distance is equal to a single stair step width. Typically, to handle process variations, the width of a single stair is wider than what would be the case in a traditional planar process to ensure that vias (added later in the process) are guaranteed to and upon (i.e., within the footprint of) their respective stair step. Again, oxide layers are anisotropically etched (etchOx2) to the top of the next polysilicon layers (Step f) and etch on through (etchPoly2) the now exposed polysilicon to the next underlying oxide layers (Step g), noting that the exposed first stair step etches down to the second layer, while the newly-exposed second stair step etches down to the first poly layer. This sequence of pull-back, oxide and poly etch is repeated until the entire stack has been etched into a terraced stair-step pattern (FIG. 3h). Finally, a thick dioxide layer is deposited (depositOx) on top of the entire staircase and planarized (e.g., by CMP) and vias are photographically patterned (photoVia1) and etched (etchVia1) down to their respective polysilicon layer (the etch is selective to attach the oxide much faster than polysilicon, so each via opening effectively stops when a polysilicon layer is reached; such etches are well known to those skilled in the art). These vias openings are then filled (depositVia1) with conductive material (such as tungsten or polysilicon) and planarized (e.g., by CMP) to bring the connections to the surface where they can be wired to other vias that connect them down to the logic on the substrate (additional photo-lithographic patterning, etching, depositing and planarizing steps).
The total number of etch steps for this part of the process, where L is the number of layers, is defined by:L(etchMask+etchOxide+etchPoly)+deposit+CMP+photoVia+etchVia+depositVia+CMPVia 
A 32 layer device would therefore have at least 96 etch steps and total over 100 process steps for this part of the process. Present day volume production semiconductor processes use pull-back etch steps no more than once and the cumulative errors can be problematic. As a result, the stair step formation sequence is typically broken up into groups resulting in the actual number of steps being even higher.
This etch sequence uses a surface hard mask to create a stair step formation on the one side of the array, but because the hard mask naturally has more than one edge of its own (i.e., a square hard mask has four sides), this stair step structure is formed on sides where it is not needed and the area associated with these other stair step structures can be wasted area resulting in a larger die size and greater cost per bit. Also, the stair steps must be larger than their associated vias, to account for the potential cumulative errors from the pull back etches resulting in an even greater die size. Lastly, the need to bring the vias to the surface, route them over to the edge beyond the stair step structure and then back down to the substrate (rather than having the vias simply drop down from each stair step directly to the substrate) even further increases the die size and cost per bit.
The present invention is a solution to the WL and BL resistance problem to enable larger arrays and greater numbers of 3-D stacking layers. The present invention is also a stair-step forming solution that can constrain the size of the step to being only two critical dimension (CD) features in width while limiting the creating of the stair step structure to be formed only where needed and with the via connection to the stair step dropping directly down to the substrate without additional routing. The present invention is also a solution that enables operating a cross-point array in a bipolar manner.